diff options
| author |   Andy Yan <andy.yan@rock-chips.com> | 2014-12-05 14:31:53 +0800 |
|---|---|---|
| committer |   Philipp Zabel <p.zabel@pengutronix.de> | 2015-01-07 18:31:59 +0100 |
| commit | d346c14eeea97898bb55e3432ca391cc05ceabe7 (patch) | |
| tree | 448bc2d7665ca08c6987baa0da3261b866d052d6 | |
| parent | drm: bridge/dw_hdmi: clear i2cmphy_stat0 reg in hdmi_phy_wait_i2c_done (diff) | |
| download | linux-dev-d346c14eeea97898bb55e3432ca391cc05ceabe7.tar.xz linux-dev-d346c14eeea97898bb55e3432ca391cc05ceabe7.zip | |
drm: bridge/dw_hdmi: add function dw_hdmi_phy_enable_spare
RK3288 HDMI will not work without the spare bit of
HDMI_PHY_CONF0 enable
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| -rw-r--r-- | drivers/gpu/drm/bridge/dw_hdmi.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/dw_hdmi.h | 3 |
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index d39dccd41e5a..3a97c8419d4f 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -713,6 +713,13 @@ static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) HDMI_PHY_CONF0_ENTMDS_MASK); } +static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable) +{ + hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, + HDMI_PHY_CONF0_SPARECTRL_OFFSET, + HDMI_PHY_CONF0_SPARECTRL_MASK); +} + static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) { hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, diff --git a/drivers/gpu/drm/bridge/dw_hdmi.h b/drivers/gpu/drm/bridge/dw_hdmi.h index baa7849851d4..175dbc89a824 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.h +++ b/drivers/gpu/drm/bridge/dw_hdmi.h @@ -837,7 +837,8 @@ enum { HDMI_PHY_CONF0_PDZ_OFFSET = 7, HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, - HDMI_PHY_CONF0_SPARECTRL = 0x20, + HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, + HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, |