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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2015-04-27 13:41:15 +0100 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-05-20 11:25:45 +0200 |
| commit | d94b5030d26b4f45510a092262bc2b542a00bd7c (patch) | |
| tree | 68481d946955c5b7536a3341d4964e42da6de78c | |
| parent | drm/i915: Remove domain flubbing from i915_gem_object_finish_gpu() (diff) | |
| download | linux-dev-d94b5030d26b4f45510a092262bc2b542a00bd7c.tar.xz linux-dev-d94b5030d26b4f45510a092262bc2b542a00bd7c.zip | |
drm/i915: Ensure cache flushes prior to doing CS flips
Synchronising to an object active on the same ring is a no-op, for the
benefit of execbuffer scheduler. However, for CS flips this means that
we can forgo checking whether the last write request of the object is
actually queued and more importantly whether the cache flush for the
write was emitted.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c890e03939fa..3c8801cecd3f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11040,6 +11040,12 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, i915_gem_request_assign(&work->flip_queued_req, obj->last_write_req); } else { + if (obj->last_write_req) { + ret = i915_gem_check_olr(obj->last_write_req); + if (ret) + goto cleanup_unpin; + } + ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags); if (ret) |