diff options
| author |   Jake Wang <haonan.wang2@amd.com> | 2021-10-01 16:46:49 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-10-19 17:20:09 -0400 |
| commit | dd706b20934f8890ab3f2567a589d99df0503868 (patch) | |
| tree | c405a9017505865000b55681daa1d1f9931e4c6d | |
| parent | drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le (diff) | |
| download | linux-dev-dd706b20934f8890ab3f2567a589d99df0503868.tar.xz linux-dev-dd706b20934f8890ab3f2567a589d99df0503868.zip | |
drm/amd/display: Removed z10 save after dsc disable
[Why & How]
Z10 save is done during PSR and bootup.
DSC disable does not need to save for Z10.
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c index fee385e37c9b..65f66687af4c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -317,10 +317,6 @@ void dcn31_dsc_pg_control( if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( hws->ctx->dc->res_pool->dccg, dsc_inst); - -#if defined(CONFIG_DRM_AMD_DC_DCN) - dc_z10_save_init(hws->ctx->dc); -#endif } } |