diff options
| author |   Ben Skeggs <bskeggs@redhat.com> | 2013-11-28 12:34:13 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-01-23 13:38:52 +1000 |
| commit | e7084c669b4fbbc695116cb63a7e2c9360706220 (patch) | |
| tree | 303bdeb454aba7cbd1df28eae1124759f175311d | |
| parent | drm/nve0/fb/gddr5: switch off some other random bit at some point (diff) | |
drm/nve0/fb/gddr5: fix calculation of RDQS setting
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index ebc314bdc412..b0b9939c2098 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c @@ -999,6 +999,7 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) if (ram_have(fuc, mr[i])) ram->base.mr[i] = ram_rd32(fuc, mr[i]); } + ram->base.freq = freq; switch (ram->base.type) { case NV_MEM_TYPE_DDR3: |