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| author |   Peter Zijlstra <peterz@infradead.org> | 2022-03-08 16:30:42 +0100 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-03-15 10:32:41 +0100 |
| commit | e8d61bdf0fdfaeaf35fb5a63d6e67e60038b88e0 (patch) | |
| tree | abb9c44d8701c1b9ba8707b0fce6804d527ae58c | |
| parent | x86/ibt,ftrace: Annotate ftrace code patching (diff) | |
| download | linux-dev-e8d61bdf0fdfaeaf35fb5a63d6e67e60038b88e0.tar.xz linux-dev-e8d61bdf0fdfaeaf35fb5a63d6e67e60038b88e0.zip | |
x86/ibt,sev: Annotations
No IBT on AMD so far.. probably correct, who knows.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Josh Poimboeuf <jpoimboe@redhat.com>
Link: https://lore.kernel.org/r/20220308154318.995109889@infradead.org
| -rw-r--r-- | arch/x86/entry/entry_64.S | 1 | ||||
| -rw-r--r-- | arch/x86/entry/entry_64_compat.S | 1 | ||||
| -rw-r--r-- | arch/x86/kernel/head_64.S | 2 |
3 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index d76f14f581f7..6e5399104abd 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -95,6 +95,7 @@ SYM_CODE_START(entry_SYSCALL_64) movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL) + ANNOTATE_NOENDBR /* Construct struct pt_regs on stack */ pushq $__USER_DS /* pt_regs->ss */ diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S index 74208a1236b3..4fdb007cddbd 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -214,6 +214,7 @@ SYM_CODE_START(entry_SYSCALL_compat) movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp SYM_INNER_LABEL(entry_SYSCALL_compat_safe_stack, SYM_L_GLOBAL) + ANNOTATE_NOENDBR /* Construct struct pt_regs on stack */ pushq $__USER32_DS /* pt_regs->ss */ diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 462cc1e18919..b8e3019547a5 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -332,6 +332,7 @@ SYM_CODE_END(start_cpu0) */ SYM_CODE_START_NOALIGN(vc_boot_ghcb) UNWIND_HINT_IRET_REGS offset=8 + ENDBR /* Build pt_regs */ PUSH_AND_CLEAR_REGS @@ -439,6 +440,7 @@ SYM_CODE_END(early_idt_handler_common) */ SYM_CODE_START_NOALIGN(vc_no_ghcb) UNWIND_HINT_IRET_REGS offset=8 + ENDBR /* Build pt_regs */ PUSH_AND_CLEAR_REGS |