diff options
| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-08-27 13:06:15 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-08-28 14:05:31 +0100 |
| commit | e8f6b4952ec54a9d7e43f908d39dc168b0310599 (patch) | |
| tree | 3b39a59060b2b142c260e49b1e7734ef093eec2d | |
| parent | drm/i915/selftests: Try to recycle context allocations (diff) | |
drm/i915/execlists: Flush the post-sync breadcrumb write harder
Quite rarely we see that the CS completion event fires before the
breadcrumb is coherent, which presumably is a result of the CS_STALL not
waiting for the post-sync operation. Try throwing in a DC_FLUSH into
the following pipecontrol to see if that makes any difference.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190827120615.31390-1-chris@chris-wilson.co.uk
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_lrc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index a141e9e37bf7..171d5205962c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2923,8 +2923,10 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) PIPE_CONTROL_DC_FLUSH_ENABLE); /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */ + /* XXX DC_FLUSH for post-sync write? (cf early context-switch bug) */ cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_FLUSH_ENABLE | + PIPE_CONTROL_DC_FLUSH_ENABLE | PIPE_CONTROL_CS_STALL, 0); |