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| author |   Enric Balletbo i Serra <enric.balletbo@collabora.com> | 2020-07-09 11:05:29 +0200 |
|---|---|---|
| committer |   Chanwoo Choi <cw00.choi@samsung.com> | 2020-07-30 17:22:57 +0900 |
| commit | ed279529754d0c94115de5317e369d25468547c9 (patch) | |
| tree | 8b7bb58976bf4a3129d6ce2c67bd8829fc566b08 | |
| parent | PM / devfreq: tegra: Add Dmitry as a maintainer (diff) | |
| download | linux-dev-ed279529754d0c94115de5317e369d25468547c9.tar.xz linux-dev-ed279529754d0c94115de5317e369d25468547c9.zip | |
dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle
The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU
general register files to know the DRAM type, so add a phandle to the
syscon that manages these registers.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gaël PORTAY <gael.portay@collabora.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
| -rw-r--r-- | Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt index 0ec68141f85a..a10d1f6d85c6 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -18,6 +18,8 @@ Optional properties: format depends on the interrupt controller. It should be a DCF interrupt. When DDR DVFS finishes a DCF interrupt is triggered. +- rockchip,pmu: Phandle to the syscon managing the "PMU general register + files". Following properties relate to DDR timing: |