diff options
| author |   Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> | 2013-10-14 09:49:25 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2014-01-22 20:18:57 +0100 |
| commit | f6ba061060f3442278d169a22db4469eed2ef1d3 (patch) | |
| tree | c747bb6aa91e492e746fa1e8438afc2482da48d4 | |
| parent | MIPS: Add printing of ES bit for Imgtec cores when cache error occurs. (diff) | |
| download | linux-dev-f6ba061060f3442278d169a22db4469eed2ef1d3.tar.xz linux-dev-f6ba061060f3442278d169a22db4469eed2ef1d3.zip | |
MIPS: Malta: Remove ttyS2 serial for CMP platforms
Commit 225ae5fd9a320e22841410049c3bdb6cf14a5841
"MIPS: Malta: Fix interupt number of CBUS UART"
fixed the IRQ number for the ttyS2 CBUS UART. However, this now
conflicts with the GIC IPI1 interrupt in CMP platforms. The Malta
interrupt code arbitrarily binds IPIs to INT2 and INT3 and since
ttyS2 uses the INT2 IRQ line, closing the device disables the
INT2 interrupt and this effectively disables the IPI1 interrupt
as well. This patch is mainly a workaround until the Malta code
is fixed properly.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6045/
| -rw-r--r-- | arch/mips/mti-malta/malta-platform.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c index 132f8663825e..e1dd1c1d3fde 100644 --- a/arch/mips/mti-malta/malta-platform.c +++ b/arch/mips/mti-malta/malta-platform.c @@ -47,6 +47,7 @@ static struct plat_serial8250_port uart8250_data[] = { SMC_PORT(0x3F8, 4), SMC_PORT(0x2F8, 3), +#ifndef CONFIG_MIPS_CMP { .mapbase = 0x1f000900, /* The CBUS UART */ .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2, @@ -55,6 +56,7 @@ static struct plat_serial8250_port uart8250_data[] = { .flags = CBUS_UART_FLAGS, .regshift = 3, }, +#endif { }, }; |