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| author |   Nicholas Piggin <npiggin@gmail.com> | 2019-06-28 15:33:22 +1000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2019-07-02 21:39:48 +1000 |
| commit | fbc50063a2358f685deaa2f8370a55e3df5ef3ab (patch) | |
| tree | cd38c8be263021d00bba3b3dbe52818e99982d49 | |
| parent | powerpc/64s/exception: avoid SPR RAW scoreboard stall in real mode entry (diff) | |
| download | linux-dev-fbc50063a2358f685deaa2f8370a55e3df5ef3ab.tar.xz linux-dev-fbc50063a2358f685deaa2f8370a55e3df5ef3ab.zip | |
powerpc/64s/exception: mtmsrd L=1 cleanup
All supported 64s CPUs support mtmsrd L=1 instruction, so a cleanup
can be made in sreset and mce handlers.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
| -rw-r--r-- | arch/powerpc/kernel/exceptions-64s.S | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 3735b9d1bb65..33c253fe8a68 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -882,11 +882,8 @@ EXC_COMMON_BEGIN(system_reset_common) addi r3,r1,STACK_FRAME_OVERHEAD bl system_reset_exception - /* This (and MCE) can be simplified with mtmsrd L=1 */ /* Clear MSR_RI before setting SRR0 and SRR1. */ - li r0,MSR_RI - mfmsr r9 - andc r9,r9,r0 + li r9,0 mtmsrd r9,1 /* @@ -1081,9 +1078,7 @@ EXC_COMMON_BEGIN(machine_check_common) #define MACHINE_CHECK_HANDLER_WINDUP \ /* Clear MSR_RI before setting SRR0 and SRR1. */\ - li r0,MSR_RI; \ - mfmsr r9; /* get MSR value */ \ - andc r9,r9,r0; \ + li r9,0; \ mtmsrd r9,1; /* Clear MSR_RI */ \ /* Move original SRR0 and SRR1 into the respective regs */ \ ld r9,_MSR(r1); \ |