diff options
| author |   Likun Gao <Likun.Gao@amd.com> | 2019-08-02 15:18:57 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-08-06 15:04:40 -0500 |
| commit | 72cda9bb5e219aea0f2f62f56ae05198c59022a7 (patch) | |
| tree | e4087457295a20e12d96abceb14b56d247336db3 /CREDITS | |
| parent | drm/amd/powerplay: correct navi10 vcn powergate (diff) | |
| download | linux-dev-72cda9bb5e219aea0f2f62f56ae05198c59022a7.tar.xz linux-dev-72cda9bb5e219aea0f2f62f56ae05198c59022a7.zip | |
drm/amdgpu: pin the csb buffer on hw init for gfx v8
Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Tested-by: Paul Gover <pmw.gover@yahoo.co.uk>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'CREDITS')
0 files changed, 0 insertions, 0 deletions