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| author |   Anshuman Khandual <anshuman.khandual@arm.com> | 2021-04-05 17:43:05 +0100 |
|---|---|---|
| committer |   Mathieu Poirier <mathieu.poirier@linaro.org> | 2021-04-06 16:05:38 -0600 |
| commit | b20f34aec776f4c735cd3a899e9bc3333463848a (patch) | |
| tree | 24e722497512137a0871e5253194b62c3232ccc2 /Documentation/ABI/testing | |
| parent | coresight: sink: Add TRBE driver (diff) | |
| download | linux-dev-b20f34aec776f4c735cd3a899e9bc3333463848a.tar.xz linux-dev-b20f34aec776f4c735cd3a899e9bc3333463848a.zip | |
Documentation: coresight: trbe: Sysfs ABI description
Add sysfs ABI documentation for the TRBE devices.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
[ Split from the TRBE driver patch ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210405164307.1720226-19-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'Documentation/ABI/testing')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe b/Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe new file mode 100644 index 000000000000..ad3bbc6fa751 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe @@ -0,0 +1,14 @@ +What: /sys/bus/coresight/devices/trbe<cpu>/align +Date: March 2021 +KernelVersion: 5.13 +Contact: Anshuman Khandual <anshuman.khandual@arm.com> +Description: (Read) Shows the TRBE write pointer alignment. This value + is fetched from the TRBIDR register. + +What: /sys/bus/coresight/devices/trbe<cpu>/flag +Date: March 2021 +KernelVersion: 5.13 +Contact: Anshuman Khandual <anshuman.khandual@arm.com> +Description: (Read) Shows if TRBE updates in the memory are with access + and dirty flag updates as well. This value is fetched from + the TRBIDR register. |