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| author |   Marc Zyngier <marc.zyngier@arm.com> | 2018-12-06 17:31:25 +0000 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2018-12-10 12:20:42 +0000 |
| commit | eb036ad2ddf008309ea25e34470898c8cd122f6b (patch) | |
| tree | 6b9abe02821fd11504394c7708ab021e7cc23a3f /Documentation/arm64/silicon-errata.txt | |
| parent | arm64: KVM: Add synchronization on translation regime change for erratum 1165522 (diff) | |
| download | linux-dev-eb036ad2ddf008309ea25e34470898c8cd122f6b.tar.xz linux-dev-eb036ad2ddf008309ea25e34470898c8cd122f6b.zip | |
arm64: KVM: Handle ARM erratum 1165522 in TLB invalidation
In order to avoid TLB corruption whilst invalidating TLBs on CPUs
affected by erratum 1165522, we need to prevent S1 page tables
from being usable.
For this, we set the EL1 S1 MMU on, and also disable the page table
walker (by setting the TCR_EL1.EPD* bits to 1).
This ensures that once we switch to the EL1/EL0 translation regime,
speculated AT instructions won't be able to parse the page tables.
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/arm64/silicon-errata.txt')
0 files changed, 0 insertions, 0 deletions