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| author |   Paolo Bonzini <pbonzini@redhat.com> | 2014-08-05 09:47:45 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-08-05 09:47:45 +0200 |
| commit | 5d5768660539b6d0da0d46113ffb0676540579a6 (patch) | |
| tree | c0cd7a918fc7371c5f5b1b9b04c6358966850277 /Documentation/arm64 | |
| parent | Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux (diff) | |
| parent | arm64: KVM: fix 64bit CP15 VM access for 32bit guests (diff) | |
| download | linux-dev-5d5768660539b6d0da0d46113ffb0676540579a6.tar.xz linux-dev-5d5768660539b6d0da0d46113ffb0676540579a6.zip | |
Merge tag 'kvm-arm-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm
KVM/ARM New features for 3.17 include:
- Fixes and code refactoring for stage2 kvm MMU unmap_range
- Support unmapping IPAs on deleting memslots for arm and arm64
- Support MMIO mappings in stage2 faults
- KVM VGIC v2 emulation on GICv3 hardware
- Big-Endian support for arm/arm64 (guest and host)
- Debug Architecture support for arm64 (arm32 is on Christoffer's todo list)
Conflicts:
virt/kvm/arm/vgic.c [last minute cherry-pick from 3.17 to 3.16]
Diffstat (limited to 'Documentation/arm64')
| -rw-r--r-- | Documentation/arm64/booting.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index 85af34d55cee..f3c05b5f9f08 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -168,6 +168,14 @@ Before jumping into the kernel, the following conditions must be met: the kernel image will be entered must be initialised by software at a higher exception level to prevent execution in an UNKNOWN state. + For systems with a GICv3 interrupt controller: + - If EL3 is present: + ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. + ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. + - If the kernel is entered at EL1: + ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 + ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. |