path: root/Documentation/arm64
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authorMark Brown <broonie@kernel.org>2021-05-12 17:23:50 +0100
committerWill Deacon <will@kernel.org>2021-05-25 19:05:28 +0100
commitca940790d2ddc91e976f1e9e685052a54a1c50cf (patch)
treea4ccb198bcf5276a73ebe3eaef4e51c8e8b092db /Documentation/arm64
parentLinux 5.13-rc3 (diff)
arm64: Document requirement for access to FEAT_HCX
v8.7 of the architecture introduced FEAT_HCX which adds an additional hypervisor configuration register HCRX_EL2. Even though Linux does not currently make use of this feature let's document that the EL3 trap for access to the register should be disabled so that we are able to make use of it in future. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20210512162350.20349-1-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'Documentation/arm64')
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 18b8cc1bf32c..a9192e7a231b 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -277,6 +277,12 @@ Before jumping into the kernel, the following conditions must be met:
- SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
+ For CPUs with support for HCRX_EL2 (FEAT_HCX) present:
+ - If EL3 is present and the kernel is entered at EL2:
+ - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
For CPUs with Advanced SIMD and floating point support:
- If EL3 is present: