path: root/Documentation/arm64
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authorMark Brown <broonie@kernel.org>2021-10-26 12:18:02 +0100
committerWill Deacon <will@kernel.org>2021-10-28 09:30:15 +0100
commitd198c77b7fab13d4def83c038807f6967f857acc (patch)
treef757a199d11cb1ec8a2cbed9135416574708506e /Documentation/arm64
parentarm64: ftrace: use function_nocfi for _mcount as well (diff)
arm64: Document boot requirements for FEAT_SME_FA64
The EAC1 release of the SME specification adds the FA64 feature which requires enablement at higher ELs before lower ELs can use it. Document what we require from higher ELs in our boot requirements. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20211026111802.12853-1-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'Documentation/arm64')
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 3f9d86557c5e..52d060caf8bb 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -340,6 +340,16 @@ Before jumping into the kernel, the following conditions must be met:
- SMCR_EL2.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
+ For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64)
+ - If EL3 is present:
+ - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
+ - If the kernel is entered at EL1 and EL2 is present:
+ - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level. Where the values documented