|author||Marc Zyngier <firstname.lastname@example.org>||2021-08-12 20:02:13 +0100|
|committer||Catalin Marinas <email@example.com>||2021-08-24 16:44:23 +0100|
|parent||arm64: head: avoid over-mapping in map_memory (diff)|
arm64: Document the requirement for SCR_EL3.HCE
It is amazing that we never documented this absolutely basic requirement: if you boot the kernel at EL2, you'd better enable the HVC instruction from EL3. Really, just do it. Signed-off-by: Marc Zyngier <firstname.lastname@example.org> Acked-by: Mark Rutland <email@example.com> Link: https://firstname.lastname@example.org Signed-off-by: Catalin Marinas <email@example.com>
Diffstat (limited to 'Documentation/arm64')
1 files changed, 11 insertions, 4 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 5822d6da9fa6..3f9d86557c5e 100644
@@ -207,10 +207,17 @@ Before jumping into the kernel, the following conditions must be met:
software at a higher exception level to prevent execution in an UNKNOWN
- - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
- executing on.
- - The value of SCR_EL3.FIQ must be the same as the one present at boot
- time whenever the kernel is executing.
+ For all systems:
+ - If EL3 is present:
+ - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
+ executing on.
+ - The value of SCR_EL3.FIQ must be the same as the one present at boot
+ time whenever the kernel is executing.
+ - If EL3 is present and the kernel is entered at EL2:
+ - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
For systems with a GICv3 interrupt controller to be used in v3 mode:
- If EL3 is present: