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| author |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-07-26 13:23:10 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-07-26 13:43:33 +0200 |
| commit | af055598542670c8533a58582813b1419949cae0 (patch) | |
| tree | 901fa1bf635d5c1e91d08f9f4c2e4943516dbb71 /Documentation/devicetree/bindings/arm/cci.txt | |
| parent | drm/syncobj: Fix kerneldoc (diff) | |
| parent | Merge tag 'drm-intel-next-2017-07-17' of git://anongit.freedesktop.org/git/drm-intel into drm-next (diff) | |
| download | linux-dev-af055598542670c8533a58582813b1419949cae0.tar.xz linux-dev-af055598542670c8533a58582813b1419949cae0.zip | |
Merge airlied/drm-next into drm-misc-next
I need this to be able to apply the deferred fbdev setup patches, I
need the relevant prep work that landed through the drm-intel tree.
Also squash in conflict fixup from Laurent Pinchart.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/cci.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/cci.txt | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt index 0f2153e8fa7e..9600761f2d5b 100644 --- a/Documentation/devicetree/bindings/arm/cci.txt +++ b/Documentation/devicetree/bindings/arm/cci.txt @@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global control register space and multiple sets of interface control registers, one per slave interface. -Bindings for the CCI node follow the ePAPR standard, available from: - -www.power.org/documentation/epapr-version-1-1/ - -with the addition of the bindings described in this document which are -specific to ARM. - * CCI interconnect node Description: Describes a CCI cache coherent Interconnect component @@ -50,10 +43,10 @@ specific to ARM. as a tuple of cells, containing child address, parent address and the size of the region in the child address space. - Definition: A standard property. Follow rules in the ePAPR for - hierarchical bus addressing. CCI interfaces - addresses refer to the parent node addressing - scheme to declare their register bases. + Definition: A standard property. Follow rules in the Devicetree + Specification for hierarchical bus addressing. CCI + interfaces addresses refer to the parent node + addressing scheme to declare their register bases. CCI interconnect node can define the following child nodes: |