diff options
author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2016-03-15 16:54:45 -0700 |
---|---|---|
committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2016-03-15 16:54:45 -0700 |
commit | 245f0db0de926601353776085e6f6a4c974c5615 (patch) | |
tree | b493e9e726f4a898041f7861d0df328aa1a348a1 /Documentation/devicetree/bindings/clock/dove-divider-clock.txt | |
parent | Input: synaptics-rmi4 - using logical instead of bitwise AND (diff) | |
parent | Linux 4.5 (diff) | |
download | linux-dev-245f0db0de926601353776085e6f6a4c974c5615.tar.xz linux-dev-245f0db0de926601353776085e6f6a4c974c5615.zip |
Merge tag 'v4.5' into next
Merge with Linux 4.5 to get PROPERTY_ENTRY_INTEGER() that is needed to
fix pxa/raumfeld rotary encoder properties.
Diffstat (limited to 'Documentation/devicetree/bindings/clock/dove-divider-clock.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/dove-divider-clock.txt | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/dove-divider-clock.txt b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt new file mode 100644 index 000000000000..e3eb0f657c5e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt @@ -0,0 +1,28 @@ +PLL divider based Dove clocks + +Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide +high speed clocks for a number of peripherals. These dividers are part of +the PMU, and thus this node should be a child of the PMU node. + +The following clocks are provided: + +ID Clock +------------- +0 AXI bus clock +1 GPU clock +2 VMeta clock +3 LCD clock + +Required properties: +- compatible : shall be "marvell,dove-divider-clock" +- reg : shall be the register address of the Core PLL and Clock Divider + Control 0 register. This will cover that register, as well as the + Core PLL and Clock Divider Control 1 register. Thus, it will have + a size of 8. +- #clock-cells : from common clock binding; shall be set to 1 + +divider_clk: core-clock@0064 { + compatible = "marvell,dove-divider-clock"; + reg = <0x0064 0x8>; + #clock-cells = <1>; +}; |