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| author |   Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2015-03-23 09:18:27 -0700 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2015-03-23 09:18:27 -0700 |
| commit | 188933ac139a6f8ab06cad369bd0200af947b00d (patch) | |
| tree | c4c107528fcf6b82e32a93b0596e13eea7aa9385 /Documentation/devicetree/bindings/clock/exynos7-clock.txt | |
| parent | Input: sun4i-ts - allow controlling filter and sensitivity via DT (diff) | |
| parent | Linux 4.0-rc5 (diff) | |
| download | linux-dev-188933ac139a6f8ab06cad369bd0200af947b00d.tar.xz linux-dev-188933ac139a6f8ab06cad369bd0200af947b00d.zip | |
Merge tag 'v4.0-rc5' into next
Merge with the latest upstream to synchronize Synaptics changes
and bring in new infrastructure pieces.
Conflicts:
drivers/input/mouse/synaptics.c
Diffstat (limited to 'Documentation/devicetree/bindings/clock/exynos7-clock.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/exynos7-clock.txt | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt index 6d3d5f80c1c3..6bf1e7493f61 100644 --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt @@ -34,6 +34,8 @@ Required Properties for Clock Controller: - "samsung,exynos7-clock-peris" - "samsung,exynos7-clock-fsys0" - "samsung,exynos7-clock-fsys1" + - "samsung,exynos7-clock-mscl" + - "samsung,exynos7-clock-aud" - reg: physical base address of the controller and the length of memory mapped region. @@ -53,6 +55,7 @@ Input clocks for top0 clock controller: - dout_sclk_bus1_pll - dout_sclk_cc_pll - dout_sclk_mfc_pll + - dout_sclk_aud_pll Input clocks for top1 clock controller: - fin_pll @@ -76,6 +79,14 @@ Input clocks for peric1 clock controller: - sclk_uart1 - sclk_uart2 - sclk_uart3 + - sclk_spi0 + - sclk_spi1 + - sclk_spi2 + - sclk_spi3 + - sclk_spi4 + - sclk_i2s1 + - sclk_pcm1 + - sclk_spdif Input clocks for peris clock controller: - fin_pll @@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller: - dout_aclk_fsys1_200 - dout_sclk_mmc0 - dout_sclk_mmc1 + +Input clocks for aud clock controller: + - fin_pll + - fout_aud_pll |