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| author |   Tang Yuantian <Yuantian.Tang@freescale.com> | 2015-01-15 14:03:41 +0800 |
|---|---|---|
| committer |   Michael Turquette <mturquette@linaro.org> | 2015-01-20 10:09:12 -0800 |
| commit | 93a17c058f610398739c8b930ff3c83a0c0b0120 (patch) | |
| tree | bdfabfc3da30d61591792629b621a495d488395a /Documentation/devicetree/bindings/clock/qoriq-clock.txt | |
| parent | clock: redefine variable clocks_per_pll as a struct member (diff) | |
| download | linux-dev-93a17c058f610398739c8b930ff3c83a0c0b0120.tar.xz linux-dev-93a17c058f610398739c8b930ff3c83a0c0b0120.zip | |
clk: ppc-corenet: rename driver to clk-qoriq
Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/qoriq-clock.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qoriq-clock.txt | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 266ff9d23229..df4a259a6898 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -1,6 +1,6 @@ -* Clock Block on Freescale CoreNet Platforms +* Clock Block on Freescale QorIQ Platforms -Freescale CoreNet chips take primary clocking input from the external +Freescale qoriq chips take primary clocking input from the external SYSCLK signal. The SYSCLK input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including @@ -29,6 +29,7 @@ Required properties: * "fsl,t4240-clockgen" * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" + * "fsl,ls1021a-clockgen" Chassis clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks |