Merge tag 'devicetree-for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:

 - Refine reserved memory nomap handling

 - Merge some PCI and non-PCI address handling implementations

 - Simplify of_address.h header ifdefs

 - Improve printk handling of some 64-bit types

 - Convert adi,adv7511, Arm ccree, Arm SCMI, Arm SCU, Arm TWD timer, Arm
   VIC, arm,sbsa-gwdt, Arm/Amlogic SCPI, Aspeed I2C, Broadcom iProc PWM,
   linaro,optee-tz, MDIO GPIO, Mediatek RNG, MTD physmap, NXP
   pcf8563/pcf85263/pcf85363, Renesas TPU, renesas,emev2-smu,
   renesas,r9a06g032-sysctrl, sysc-rmobile, Tegra20 EMC, TI AM56 PCI, TI
   OMAP mailbox, TI SCI bindings, virtio-mmio, Zynq FPGA, and ZynqMP RTC
   to DT schema

 - Convert mux and mux controller bindings to schema. This includes MDIO
   IIO, and I2C muxes.

 - Add Arm PL031 RTC binding schema

 - Add vendor prefixes for StarFive Technology Co. Ltd. and Insignal Ltd

 - Fix some stale doc references

 - Remove stale property-units.txt. Superseded by schema in dt-schema
   repo.

 - Fixes for 'unevaluatedProperties' handling (enabled with experimental
   json-schema support)

 - Drop redundant usage of minItems and maxItems across the tree

 - Update some examples to use bindings with a schema

* tag 'devicetree-for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (83 commits)
  dt-bindings: Fix 'unevaluatedProperties' errors in DT graph users
  dt-bindings: display: renesas,du: Fix 'ports' reference
  dt-bindings: media: adv7180: Add missing video-interfaces.yaml reference
  dt-bindings: crypto: ccree: Convert to json-schema
  dt-bindings: fpga: zynq: convert bindings to YAML
  dt-bindings: rtc: zynqmp: convert bindings to YAML
  dt-bindings: interrupt-controller: Convert ARM VIC to json-schema
  of: of_reserved_mem: mark nomap memory instead of removing
  of: of_reserved_mem: only call memblock_free for normal reserved memory
  dt-bindings: Drop redundant minItems/maxItems
  dt-bindings: spmi: Correct 'reg' schema
  of: reserved-memory: Add stub for RESERVEDMEM_OF_DECLARE()
  dt-bindings: clk: vc5: Fix example
  dt-bindings: timer: renesas,tmu: add r8a779a0 TMU support
  dt-bindings: drm: bridge: adi,adv7511.txt: convert to yaml
  dt-bindings: PCI: ti,am65: Convert PCIe host/endpoint mode dt-bindings to YAML
  of: Remove superfluous casts when printing u64 values
  of: Fix truncation of memory sizes on 32-bit platforms
  dt-bindings: rtc: nxp,pcf8563: Absorb pcf85263/pcf85363 bindings
  dt-bindings: pwm: Use examples with documented/matching schema
  ...

1 files changed, 140 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml
new file mode 100644
index 000000000000..4d9a64800481
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas EMMA Mobile EV2 System Management Unit
+
+maintainers:
+  - Geert Uytterhoeven <geert+renesas@glider.be>
+  - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+  The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
+  This is not a clock provider, but clocks under SMU depend on it.
+
+properties:
+  compatible:
+    const: renesas,emev2-smu
+
+  reg:
+    maxItems: 1
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - '#address-cells'
+  - '#size-cells'
+
+patternProperties:
+  ".*sclkdiv@.*":
+    type: object
+
+    description: |
+      Function block with an input mux and a divider, which corresponds to
+      "Serial clock generator" in fig. "Clock System Overview" of the manual,
+      and "xxx frequency division setting register" (XXXCLKDIV) registers.
+      This makes internal (neither input nor output) clock that is provided
+      to input of xxxGCLK block.
+
+    properties:
+      compatible:
+        const: renesas,emev2-smu-clkdiv
+
+      reg:
+        maxItems: 1
+        description:
+          Byte offset from SMU base and Bit position in the register.
+
+      clocks:
+        minItems: 1
+        maxItems: 4
+
+      '#clock-cells':
+        const: 0
+
+    required:
+      - compatible
+      - reg
+      - clocks
+      - '#clock-cells'
+
+    additionalProperties: false
+
+  ".*sclk@.*":
+    type: object
+
+    description: |
+      Clock gating node shown as "Clock stop processing block" in the
+      fig. "Clock System Overview" of the manual.
+      Registers are "xxx clock gate control register" (XXXGCLKCTRL).
+
+    properties:
+      compatible:
+        const: renesas,emev2-smu-gclk
+
+      reg:
+        maxItems: 1
+        description:
+          Byte offset from SMU base and Bit position in the register.
+
+      clocks:
+        maxItems: 1
+
+      '#clock-cells':
+        const: 0
+
+    required:
+      - compatible
+      - reg
+      - clocks
+      - '#clock-cells'
+
+    additionalProperties: false
+
+additionalProperties: true
+
+examples:
+  - |
+    // Example of clock-tree description:
+    //
+    //  This describes a clock path in the clock tree
+    //   c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
+    clocks@e0110000 {
+            compatible = "renesas,emev2-smu";
+            reg = <0xe0110000 0x10000>;
+            #address-cells = <2>;
+            #size-cells = <0>;
+
+            c32ki: c32ki {
+                    compatible = "fixed-clock";
+                    clock-frequency = <32768>;
+                    #clock-cells = <0>;
+            };
+            pll3_fo: pll3_fo {
+                    compatible = "fixed-factor-clock";
+                    clocks = <&c32ki>;
+                    clock-div = <1>;
+                    clock-mult = <7000>;
+                    #clock-cells = <0>;
+            };
+            usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
+                    compatible = "renesas,emev2-smu-clkdiv";
+                    reg = <0x610 0>;
+                    clocks = <&pll3_fo>;
+                    #clock-cells = <0>;
+            };
+            usia_u0_sclk: usia_u0_sclk@4a0,1 {
+                    compatible = "renesas,emev2-smu-gclk";
+                    reg = <0x4a0 1>;
+                    clocks = <&usia_u0_sclkdiv>;
+                    #clock-cells = <0>;
+            };
+    };