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authorBoris BREZILLON <boris.brezillon@free-electrons.com>2015-06-18 15:46:18 +0200
committerHerbert Xu <herbert@gondor.apana.org.au>2015-06-19 22:18:02 +0800
commit51b44fc81178136bca88565dad07c067c8dc51da (patch)
treef59a15c9ae84ea0bdf05624a47bc399f0c543e03 /Documentation/devicetree/bindings/crypto/fsl-sec4.txt
parentcrypto: mv_cesa - document the clocks property (diff)
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crypto: mv_cesa - use gen_pool to reserve the SRAM memory region
The mv_cesa driver currently expects the SRAM memory region to be passed as a platform device resource. This approach implies two drawbacks: - the DT representation is wrong - the only one that can access the SRAM is the crypto engine The last point is particularly annoying in some cases: for example on armada 370, a small region of the crypto SRAM is used to implement the cpuidle, which means you would not be able to enable both cpuidle and the CESA driver. To address that problem, we explicitly define the SRAM device in the DT and then reference the sram node from the crypto engine node. Also note that the old way of retrieving the SRAM memory region is still supported, or in other words, backward compatibility is preserved. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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