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author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-06 10:49:42 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-06 10:49:42 -0700 |
commit | 39eda2aba6be642b71f2e0ad623dcb09fd9d79cf (patch) | |
tree | cd0c8f547847641af73e38aab2478f3119dee490 /Documentation/devicetree/bindings/crypto/fsl-sec6.txt | |
parent | Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial (diff) | |
parent | powerpc: Correct FSCR bit definitions (diff) | |
download | linux-dev-39eda2aba6be642b71f2e0ad623dcb09fd9d79cf.tar.xz linux-dev-39eda2aba6be642b71f2e0ad623dcb09fd9d79cf.zip |
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc updates from Ben Herrenschmidt:
"Here's the powerpc batch for this merge window. Some of the
highlights are:
- A bunch of endian fixes ! We don't have full LE support yet in that
release but this contains a lot of fixes all over arch/powerpc to
use the proper accessors, call the firmware with the right endian
mode, etc...
- A few updates to our "powernv" platform (non-virtualized, the one
to run KVM on), among other, support for bridging the P8 LPC bus
for UARTs, support and some EEH fixes.
- Some mpc51xx clock API cleanups in preparation for a clock API
overhaul
- A pile of cleanups of our old math emulation code, including better
support for using it to emulate optional FP instructions on
embedded chips that otherwise have a HW FPU.
- Some infrastructure in selftest, for powerpc now, but could be
generalized, initially used by some tests for our perf instruction
counting code.
- A pile of fixes for hotplug on pseries (that was seriously
bitrotting)
- The usual slew of freescale embedded updates, new boards, 64-bit
hiberation support, e6500 core PMU support, etc..."
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (146 commits)
powerpc: Correct FSCR bit definitions
powerpc/xmon: Fix printing of set of CPUs in xmon
powerpc/pseries: Move lparcfg.c to platforms/pseries
powerpc/powernv: Return secondary CPUs to firmware on kexec
powerpc/btext: Fix CONFIG_PPC_EARLY_DEBUG_BOOTX on ppc32
powerpc: Cleanup handling of the DSCR bit in the FSCR register
powerpc/pseries: Child nodes are not detached by dlpar_detach_node
powerpc/pseries: Add mising of_node_put in delete_dt_node
powerpc/pseries: Make dlpar_configure_connector parent node aware
powerpc/pseries: Do all node initialization in dlpar_parse_cc_node
powerpc/pseries: Fix parsing of initial node path in update_dt_node
powerpc/pseries: Pack update_props_workarea to map correctly to rtas buffer header
powerpc/pseries: Fix over writing of rtas return code in update_dt_node
powerpc/pseries: Fix creation of loop in device node property list
powerpc: Skip emulating & leave interrupts off for kernel program checks
powerpc: Add more exception trampolines for hypervisor exceptions
powerpc: Fix location and rename exception trampolines
powerpc: Add more trap names to xmon
powerpc/pseries: Add a warning in the case of cross-cpu VPA registration
powerpc: Update the 00-Index in Documentation/powerpc
...
Diffstat (limited to 'Documentation/devicetree/bindings/crypto/fsl-sec6.txt')
-rw-r--r-- | Documentation/devicetree/bindings/crypto/fsl-sec6.txt | 157 |
1 files changed, 157 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt new file mode 100644 index 000000000000..c0a20cd972e3 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt @@ -0,0 +1,157 @@ +SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM). +Currently Freescale powerpc chip C29X is embeded with SEC 6. +SEC 6 device tree binding include: + -SEC 6 Node + -Job Ring Node + -Full Example + +===================================================================== +SEC 6 Node + +Description + + Node defines the base address of the SEC 6 block. + This block specifies the address range of all global + configuration registers for the SEC 6 block. + For example, In C293, we could see three SEC 6 node. + +PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: Must include "fsl,sec-v6.0". + + - fsl,sec-era + Usage: optional + Value type: <u32> + Definition: A standard property. Define the 'ERA' of the SEC + device. + + - #address-cells + Usage: required + Value type: <u32> + Definition: A standard property. Defines the number of cells + for representing physical addresses in child nodes. + + - #size-cells + Usage: required + Value type: <u32> + Definition: A standard property. Defines the number of cells + for representing the size of physical addresses in + child nodes. + + - reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the physical + address and length of the SEC 6 configuration registers. + + - ranges + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the physical address + range of the SEC 6.0 register space (-SNVS not included). A + triplet that includes the child address, parent address, & + length. + + Note: All other standard properties (see the ePAPR) are allowed + but are optional. + +EXAMPLE + crypto@a0000 { + compatible = "fsl,sec-v6.0"; + fsl,sec-era = <6>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xa0000 0x20000>; + ranges = <0 0xa0000 0x20000>; + }; + +===================================================================== +Job Ring (JR) Node + + Child of the crypto node defines data processing interface to SEC 6 + across the peripheral bus for purposes of processing + cryptographic descriptors. The specified address + range can be made visible to one (or more) cores. + The interrupt defined for this node is controlled within + the address range of this node. + + - compatible + Usage: required + Value type: <string> + Definition: Must include "fsl,sec-v6.0-job-ring". + + - reg + Usage: required + Value type: <prop-encoded-array> + Definition: Specifies a two JR parameters: an offset from + the parent physical address and the length the JR registers. + + - interrupts + Usage: required + Value type: <prop_encoded-array> + Definition: Specifies the interrupts generated by this + device. The value of the interrupts property + consists of one interrupt specifier. The format + of the specifier is defined by the binding document + describing the node's interrupt parent. + +EXAMPLE + jr@1000 { + compatible = "fsl,sec-v6.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <49 2 0 0>; + }; + +=================================================================== +Full Example + +Since some chips may contain more than one SEC, the dtsi contains +only the node contents, not the node itself. A chip using the SEC +should include the dtsi inside each SEC node. Example: + +In qoriq-sec6.0.dtsi: + + compatible = "fsl,sec-v6.0"; + fsl,sec-era = <6>; + #address-cells = <1>; + #size-cells = <1>; + + jr@1000 { + compatible = "fsl,sec-v6.0-job-ring", + "fsl,sec-v5.2-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.4-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + }; + + jr@2000 { + compatible = "fsl,sec-v6.0-job-ring", + "fsl,sec-v5.2-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.4-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + }; + +In the C293 device tree, we add the include of public property: + + crypto@a0000 { + /include/ "qoriq-sec6.0.dtsi" + } + + crypto@a0000 { + reg = <0xa0000 0x20000>; + ranges = <0 0xa0000 0x20000>; + + jr@1000 { + interrupts = <49 2 0 0>; + }; + + jr@2000 { + interrupts = <50 2 0 0>; + }; + }; |