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author | CK Hu <ck.hu@mediatek.com> | 2016-01-04 18:36:33 +0100 |
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committer | Philipp Zabel <p.zabel@pengutronix.de> | 2016-05-06 14:20:57 +0200 |
commit | 923dd88d3cf87ed3751d3ce8a8abc43fdbb4632b (patch) | |
tree | b4c51b17ed83d9f9c0d3b4956a4ed1fbb1eb87a1 /Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt | |
parent | memory: mtk-smi: export mtk_smi_larb_get/put (diff) | |
download | linux-dev-923dd88d3cf87ed3751d3ce8a8abc43fdbb4632b.tar.xz linux-dev-923dd88d3cf87ed3751d3ce8a8abc43fdbb4632b.zip |
dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt')
-rw-r--r-- | Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt new file mode 100644 index 000000000000..2b1585a34b85 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -0,0 +1,60 @@ +Mediatek DSI Device +=================== + +The Mediatek DSI function block is a sink of the display subsystem and can +drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- +channel output. + +Required properties: +- compatible: "mediatek,<chip>-dsi" +- reg: Physical base address and length of the controller's registers +- interrupts: The interrupt signal from the function block. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must contain "engine", "digital", and "hs" +- phys: phandle link to the MIPI D-PHY controller. +- phy-names: must contain "dphy" +- port: Output port node with endpoint definitions as described in + Documentation/devicetree/bindings/graph.txt. This port should be connected + to the input port of an attached DSI panel or DSI-to-eDP encoder chip. + +MIPI TX Configuration Module +============================ + +The MIPI TX configuration module controls the MIPI D-PHY. + +Required properties: +- compatible: "mediatek,<chip>-mipi-tx" +- reg: Physical base address and length of the controller's registers +- clocks: PLL reference clock +- clock-output-names: name of the output clock line to the DSI encoder +- #clock-cells: must be <0>; +- #phy-cells: must be <0>. + +Example: + +mipi_tx0: mipi-dphy@10215000 { + compatible = "mediatek,mt8173-mipi-tx"; + reg = <0 0x10215000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; +}; + +dsi0: dsi@1401b000 { + compatible = "mediatek,mt8173-dsi"; + reg = <0 0x1401b000 0 0x1000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + + port { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; |