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| author |   Mark Brown <broonie@kernel.org> | 2015-03-10 10:37:02 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-03-10 10:37:02 +0000 |
| commit | eb5bc2a213f96bd43b5f00a625acb0c669613645 (patch) | |
| tree | 6093a86c9e704ebfed54adb426ff3079a428da93 /Documentation/devicetree/bindings/gpio/gpio.txt | |
| parent | ASoC: rt5670: Check sysclk source by private data (diff) | |
| parent | Linux 4.0-rc3 (diff) | |
| download | linux-dev-eb5bc2a213f96bd43b5f00a625acb0c669613645.tar.xz linux-dev-eb5bc2a213f96bd43b5f00a625acb0c669613645.zip | |
Merge tag 'v4.0-rc3' into asoc-rt5670
Linux 4.0-rc3
Conflicts:
sound/soc/codecs/rt5670.c
Diffstat (limited to 'Documentation/devicetree/bindings/gpio/gpio.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/gpio/gpio.txt | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index b9bd1d64cfa6..f7a158d85862 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -69,7 +69,8 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. ---------------------------------- A gpio-specifier should contain a flag indicating the GPIO polarity; active- -high or active-low. If it does, the follow best practices should be followed: +high or active-low. If it does, the following best practices should be +followed: The gpio-specifier's polarity flag should represent the physical level at the GPIO controller that achieves (or represents, for inputs) a logically asserted @@ -147,7 +148,7 @@ contains information structures as follows: numeric-gpio-range ::= <pinctrl-phandle> <gpio-base> <pinctrl-base> <count> named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>' - gpio-phandle : phandle to pin controller node. + pinctrl-phandle : phandle to pin controller node gpio-base : Base GPIO ID in the GPIO controller pinctrl-base : Base pinctrl pin ID in the pin controller count : The number of GPIOs/pins in this range |