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authorStephen Warren <swarren@nvidia.com>2012-01-04 08:39:34 +0000
committerOlof Johansson <olof@lixom.net>2012-02-06 18:21:19 -0800
commita38b84fce9d1f3b1f054409b6363d98bf019e263 (patch)
treede18976725aec6c1d0559f047a9b306ae095c224 /Documentation/devicetree/bindings/gpio
parentARM: tegra: seaboard: add EMC table to device tree (diff)
downloadlinux-dev-a38b84fce9d1f3b1f054409b6363d98bf019e263.tar.xz
linux-dev-a38b84fce9d1f3b1f054409b6363d98bf019e263.zip
dt: tegra gpio: Flesh out binding documentation
Document the required reg and interrupts properties. Add a complete example. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'Documentation/devicetree/bindings/gpio')
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio_nvidia.txt18
1 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt b/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt
index eb4b530d64e1..50b363c5b884 100644
--- a/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt
@@ -2,7 +2,25 @@ NVIDIA Tegra 2 GPIO controller
Required properties:
- compatible : "nvidia,tegra20-gpio"
+- reg : Physical base address and length of the controller's registers.
+- interrupts : The interrupt outputs from the controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
- gpio-controller : Marks the device node as a GPIO controller.
+
+Example:
+
+gpio: gpio@6000d000 {
+ compatible = "nvidia,tegra20-gpio";
+ reg = < 0x6000d000 0x1000 >;
+ interrupts = < 0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04 >;
+ #gpio-cells = <2>;
+ gpio-controller;
+};