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authorAlexandre Courbot <acourbot@nvidia.com>2016-03-28 18:23:02 +0900
committerThierry Reding <treding@nvidia.com>2016-04-26 18:40:16 +0200
commit53cafb93da6fdafc5904c27a3da83123e72e7c13 (patch)
treeb5f2091b1a52c3cfaa7af40edb75195a6f77d07d /Documentation/devicetree/bindings/gpu
parentdt-bindings: gk20a: Document iommus property (diff)
downloadlinux-dev-53cafb93da6fdafc5904c27a3da83123e72e7c13.tar.xz
linux-dev-53cafb93da6fdafc5904c27a3da83123e72e7c13.zip
dt-bindings: Add documentation for GM20B GPU
GM20B's definition is mostly similar to GK20A's, but requires an additional clock. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/gpu')
-rw-r--r--Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt29
1 files changed, 26 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index 1e3748337319..ff3db65e50de 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -1,9 +1,10 @@
-NVIDIA GK20A Graphics Processing Unit
+NVIDIA Tegra Graphics Processing Units
Required properties:
- compatible: "nvidia,<gpu>"
Currently recognized values:
- nvidia,gk20a
+ - nvidia,gm20b
- reg: Physical base address and length of the controller's registers.
Must contain two entries:
- first entry for bar0
@@ -19,6 +20,9 @@ Required properties:
- clock-names: Must include the following entries:
- gpu
- pwr
+If the compatible string is "nvidia,gm20b", then the following clock
+is also required:
+ - ref
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
@@ -27,9 +31,9 @@ Required properties:
Optional properties:
- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
-Example:
+Example for GK20A:
- gpu@0,57000000 {
+ gpu@57000000 {
compatible = "nvidia,gk20a";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
@@ -45,3 +49,22 @@ Example:
iommus = <&mc TEGRA_SWGROUP_GPU>;
status = "disabled";
};
+
+Example for GM20B:
+
+ gpu@57000000 {
+ compatible = "nvidia,gm20b";
+ reg = <0x0 0x57000000 0x0 0x01000000>,
+ <0x0 0x58000000 0x0 0x01000000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&tegra_car TEGRA210_CLK_GPU>,
+ <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
+ <&tegra_car TEGRA210_CLK_PLL_G_REF>;
+ clock-names = "gpu", "pwr", "ref";
+ resets = <&tegra_car 184>;
+ reset-names = "gpu";
+ iommus = <&mc TEGRA_SWGROUP_GPU>;
+ status = "disabled";
+ };