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| author |   Hiroshi Doyu <hdoyu@nvidia.com> | 2012-06-25 14:23:55 +0300 |
|---|---|---|
| committer |   Joerg Roedel <joerg.roedel@amd.com> | 2012-06-25 13:50:43 +0200 |
| commit | 0760e8faa960f8ee991fa4acb802db4e20661281 (patch) | |
| tree | 87fd7b7127f4758d71480809c650fdde252b9076 /Documentation/devicetree/bindings/iommu | |
| parent | iommu: Add DMA window parser, of_get_dma_window() (diff) | |
| download | linux-dev-0760e8faa960f8ee991fa4acb802db4e20661281.tar.xz linux-dev-0760e8faa960f8ee991fa4acb802db4e20661281.zip | |
iommu/tegra: smmu: Add device tree support for SMMU
The necessary info is expected to pass from DT.
For more precise resource reservation, there shouldn't be any
overlapping of register range between SMMU and MC. SMMU register
offset needs to be calculated correctly, based on its register bank.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'Documentation/devicetree/bindings/iommu')
| -rw-r--r-- | Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt new file mode 100644 index 000000000000..89fb5434b730 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt @@ -0,0 +1,21 @@ +NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) + +Required properties: +- compatible : "nvidia,tegra30-smmu" +- reg : Should contain 3 register banks(address and length) for each + of the SMMU register blocks. +- interrupts : Should contain MC General interrupt. +- nvidia,#asids : # of ASIDs +- dma-window : IOVA start address and length. +- nvidia,ahb : phandle to the ahb bus connected to SMMU. + +Example: + smmu { + compatible = "nvidia,tegra30-smmu"; + reg = <0x7000f010 0x02c + 0x7000f1f0 0x010 + 0x7000f228 0x05c>; + nvidia,#asids = <4>; /* # of ASIDs */ + dma-window = <0 0x40000000>; /* IOVA start & length */ + nvidia,ahb = <&ahb>; + }; |