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| author |   Oleksij Rempel <o.rempel@pengutronix.de> | 2018-08-03 07:29:17 +0200 |
|---|---|---|
| committer |   Jassi Brar <jaswinder.singh@linaro.org> | 2018-08-15 09:53:07 +0530 |
| commit | d6ef139c83cc562b29a5cdac270f0a562c1c8eda (patch) | |
| tree | 98f1ea7e33b5f5884d403a63e31fbc1f82f4a597 /Documentation/devicetree/bindings/mailbox | |
| parent | dt-bindings: arm: fsl: add mu binding doc (diff) | |
| download | linux-dev-d6ef139c83cc562b29a5cdac270f0a562c1c8eda.tar.xz linux-dev-d6ef139c83cc562b29a5cdac270f0a562c1c8eda.zip | |
dt-bindings: mailbox: imx-mu: add generic MU channel support
Each MU has four pairs of rx/tx data register with four rx/tx interrupts
which can also be used as a separate channel.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mailbox')
| -rw-r--r-- | Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 26 |
1 files changed, 23 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt index 90e4905dfc69..f3cf77eb5ab4 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -18,11 +18,31 @@ Messaging Unit Device Node: Required properties: ------------------- - compatible : should be "fsl,<chip>-mu", the supported chips include - imx8qxp, imx8qm. + imx6sx, imx7s, imx8qxp, imx8qm. + The "fsl,imx6sx-mu" compatible is seen as generic and should + be included together with SoC specific compatible. - reg : Should contain the registers location and length - interrupts : Interrupt number. The interrupt specifier format depends on the interrupt controller parent. -- #mbox-cells: Must be 0. Number of cells in a mailbox +- #mbox-cells: Must be 2. + <&phandle type channel> + phandle : Label name of controller + type : Channel type + channel : Channel number + + This MU support 4 type of unidirectional channels, each type + has 4 channels. A total of 16 channels. Following types are + supported: + 0 - TX channel with 32bit transmit register and IRQ transmit + acknowledgment support. + 1 - RX channel with 32bit receive register and IRQ support + 2 - TX doorbell channel. Without own register and no ACK support. + 3 - RX doorbell channel. + +Optional properties: +------------------- +- clocks : phandle to the input clock. +- fsl,mu-side-b : Should be set for side B MU. Examples: -------- @@ -30,5 +50,5 @@ lsio_mu0: mailbox@5d1b0000 { compatible = "fsl,imx8qxp-mu"; reg = <0x0 0x5d1b0000 0x0 0x10000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <0>; + #mbox-cells = <2>; }; |