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| author |   Linus Walleij <linus.walleij@linaro.org> | 2019-11-13 23:10:52 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-11-13 23:10:52 +0100 |
| commit | 1566a6a30bf4d85849bab7e389392d6d3de1530e (patch) | |
| tree | bbc979f430cb07d41f7b35524027e25e7a4b9fe6 /Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml | |
| parent | dt-bindings: pinctrl: Convert generic pin mux and config properties to schema (diff) | |
| parent | Linux 5.4-rc5 (diff) | |
| download | linux-dev-1566a6a30bf4d85849bab7e389392d6d3de1530e.tar.xz linux-dev-1566a6a30bf4d85849bab7e389392d6d3de1530e.zip | |
Merge tag 'v5.4-rc5' into devel
Linux 5.4-rc5
Diffstat (limited to 'Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml index 27f38eed389e..d3e423fcb6c2 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/allwinner,sun4i-a10-csi.yaml# +$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings @@ -27,14 +27,12 @@ properties: clocks: items: - description: The CSI interface clock - - description: The CSI module clock - description: The CSI ISP clock - description: The CSI DRAM clock clock-names: items: - const: bus - - const: mod - const: isp - const: ram @@ -89,9 +87,8 @@ examples: compatible = "allwinner,sun7i-a20-csi0"; reg = <0x01c09000 0x1000>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>, - <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; - clock-names = "bus", "mod", "isp", "ram"; + clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; + clock-names = "bus", "isp", "ram"; resets = <&ccu RST_CSI0>; port { |