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authorMaxime Ripard <maxime@cerno.tech>2019-12-13 08:40:55 +0100
committerRob Herring <robh@kernel.org>2019-12-17 19:57:14 -0600
commitfc0b90f63e7f7583813c2e86b3d0757e45882347 (patch)
tree62419f63b1a2fe2fa8cbed066a0a70f9e7ad0580 /Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml
parentdt-bindings: sram: Convert Allwinner A10 system controller to a schema (diff)
downloadlinux-dev-fc0b90f63e7f7583813c2e86b3d0757e45882347.tar.xz
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dt-bindings: media: Convert Allwinner hardware codec to a schema
The Allwinner SoCs have a hardware video codec that is supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Rob Herring <robh@kernel.org>
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diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml
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+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A10 Video Engine Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <mripard@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - allwinner,sun4i-a10-video-engine
+ - allwinner,sun5i-a13-video-engine
+ - allwinner,sun7i-a20-video-engine
+ - allwinner,sun8i-a33-video-engine
+ - allwinner,sun8i-h3-video-engine
+ - allwinner,sun50i-a64-video-engine
+ - allwinner,sun50i-h5-video-engine
+ - allwinner,sun50i-h6-video-engine
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Bus Clock
+ - description: Module Clock
+ - description: RAM Clock
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: mod
+ - const: ram
+
+ resets:
+ maxItems: 1
+
+ allwinner,sram:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: Phandle to the device SRAM
+
+ memory-region:
+ description:
+ CMA pool to use for buffers allocation instead of the default
+ CMA pool.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - allwinner,sram
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/sun7i-a20-ccu.h>
+ #include <dt-bindings/reset/sun4i-a10-ccu.h>
+
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun7i-a20-video-engine";
+ reg = <0x01c0e000 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_VE>;
+ allwinner,sram = <&ve_sram 1>;
+ };
+
+...