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authorPhilipp Zabel <p.zabel@pengutronix.de>2020-09-23 10:21:12 +0200
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2020-11-16 10:31:13 +0100
commitd7dc892dd46d8d5c733b39c6631a7f616cc95d94 (patch)
treec73979e315b9cea3bba6355694287b5346453f6d /Documentation/devicetree/bindings/media/coda.yaml
parentmedia: dt-bindings: media: ov772x: Document endpoint props (diff)
downloadlinux-dev-d7dc892dd46d8d5c733b39c6631a7f616cc95d94.tar.xz
linux-dev-d7dc892dd46d8d5c733b39c6631a7f616cc95d94.zip
media: dt-bindings: convert CODA VPU bindings to yaml
Convert to YAML and add generic IP core compatibles "cnm,codadx6", "cnm,codahx4", "cnm,coda7541", and "cnm,coda960" in addition to the SoC specific compatibles. The new generic compatibles are already used in the SoC device trees and replace the free form comments. For example: - compatible : should be "fsl,<chip>-src" for i.MX SoCs: (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27 turns into: properties: compatible: oneOf: - items: - const: fsl,imx27-vpu - const: cnm,codadx6 This allows to properly specify the secondary JPEG unit interrupt that is only present on cnm,coda960. Also add the missing "fsl,imx6dl-vpu", "cnm,coda960" compatible. The AXI bus connection to the internal SRAM is different between i.MX6Q and i.MX6DL, which requires the driver to load a different firmware depending on the SoC. Further, specify the power-domain property for i.MX6 and change the clock order from "ahb", "per" to "per", "ahb". This order is currently used in all SoC device trees. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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diff --git a/Documentation/devicetree/bindings/media/coda.yaml b/Documentation/devicetree/bindings/media/coda.yaml
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/coda.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chips&Media Coda multi-standard codec IP
+
+maintainers:
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |-
+ Coda codec IPs are present in i.MX SoCs in various versions,
+ called VPU (Video Processing Unit).
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: fsl,imx27-vpu
+ - const: cnm,codadx6
+ - items:
+ - const: fsl,imx51-vpu
+ - const: cnm,codahx4
+ - items:
+ - const: fsl,imx53-vpu
+ - const: cnm,coda7541
+ - items:
+ - enum:
+ - fsl,imx6dl-vpu
+ - fsl,imx6q-vpu
+ - const: cnm,coda960
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PER clock
+ - description: AHB interface clock
+
+ clock-names:
+ items:
+ - const: per
+ - const: ahb
+
+ resets:
+ maxItems: 1
+
+ iram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle pointing to the SRAM device node
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: cnm,coda960
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: BIT processor interrupt
+ - description: JPEG unit interrupt
+
+ interrupt-names:
+ items:
+ - const: bit
+ - const: jpeg
+ else:
+ properties:
+ interrupts:
+ items:
+ - description: BIT processor interrupt
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6dl-vpu
+ - fsl,imx6q-vpu
+ then:
+ properties:
+ power-domains:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle pointing to the PU power domain
+ maxItems: 1
+
+examples:
+ - |
+ vpu: video-codec@63ff4000 {
+ compatible = "fsl,imx53-vpu", "cnm,coda7541";
+ reg = <0x63ff4000 0x1000>;
+ interrupts = <9>;
+ clocks = <&clks 63>, <&clks 63>;
+ clock-names = "per", "ahb";
+ iram = <&ocram>;
+ };