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authorJacopo Mondi <jacopo+renesas@jmondi.org>2018-07-09 10:19:18 -0400
committerMauro Carvalho Chehab <mchehab+samsung@kernel.org>2018-07-24 14:57:06 -0400
commit75571ee0e50da56ea45a9cea3a540dd0955fa7ce (patch)
tree1307cf16f245dfa2b35ab2d95273e5ef9b5805d3 /Documentation/devicetree/bindings/media
parentmedia: dt-bindings: media: rcar-vin: Describe optional ep properties (diff)
downloadlinux-dev-75571ee0e50da56ea45a9cea3a540dd0955fa7ce.tar.xz
linux-dev-75571ee0e50da56ea45a9cea3a540dd0955fa7ce.zip
media: dt-bindings: media: Document data-enable-active property
Add 'data-enable-active' property to endpoint node properties list. The property allows to specify the polarity of the data-enable signal, which when in active state determinates when data lines have to sampled for valid pixel data. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/media')
-rw-r--r--Documentation/devicetree/bindings/media/video-interfaces.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt
index 52b7c7b57842..baf9d9756b3c 100644
--- a/Documentation/devicetree/bindings/media/video-interfaces.txt
+++ b/Documentation/devicetree/bindings/media/video-interfaces.txt
@@ -113,6 +113,8 @@ Optional endpoint properties
Note, that if HSYNC and VSYNC polarities are not specified, embedded
synchronization may be required, where supported.
- data-active: similar to HSYNC and VSYNC, specifies data line polarity.
+- data-enable-active: similar to HSYNC and VSYNC, specifies the data enable
+ signal polarity.
- field-even-active: field signal level during the even field data transmission.
- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
signal.