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authorHonghui Zhang <honghui.zhang@mediatek.com>2017-08-04 09:32:27 +0800
committerJoerg Roedel <jroedel@suse.de>2017-08-04 12:04:58 +0200
commit611de8fcf7f62718bcf9d0469ac84d66e6d89348 (patch)
treebdab88544de8cc707acd33be39c56e7290eb8da7 /Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
parentmemory: mtk-smi: add larbid handle routine (diff)
downloadlinux-dev-611de8fcf7f62718bcf9d0469ac84d66e6d89348.tar.xz
linux-dev-611de8fcf7f62718bcf9d0469ac84d66e6d89348.zip
dt-bindings: mediatek: add descriptions for larbid
This patch add larbid descritptions for mediatek's gen1 smi larb hardware. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt')
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt15
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
index 21277a56e94c..ddf46b8856a5 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
@@ -15,6 +15,9 @@ Required properties:
the register.
- "smi" : It's the clock for transfer data and command.
+Required property for mt2701:
+- mediatek,larb-id :the hardware id of this larb.
+
Example:
larb1: larb@16010000 {
compatible = "mediatek,mt8173-smi-larb";
@@ -25,3 +28,15 @@ Example:
<&vdecsys CLK_VDEC_LARB_CKEN>;
clock-names = "apb", "smi";
};
+
+Example for mt2701:
+ larb0: larb@14010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x14010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <0>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };