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authorCooper Jr., Franklin <fcooper@ti.com>2016-05-04 13:34:44 -0500
committerBoris Brezillon <boris.brezillon@free-electrons.com>2016-05-30 10:03:18 +0200
commitcabfeaa67843bf8ddda819a6129e20472053310a (patch)
tree5630fb43b2952211c2871c885d89789fbee30a66 /Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
parentmtd: nand: omap2: Support parsing dma channel information from DT (diff)
downloadlinux-dev-cabfeaa67843bf8ddda819a6129e20472053310a.tar.xz
linux-dev-cabfeaa67843bf8ddda819a6129e20472053310a.zip
ARM: OMAP2+: Update GPMC and NAND DT binding documentation
Add additional details to the GPMC NAND documentation to clarify what is needed to enable NAND DMA prefetch. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt')
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt7
1 files changed, 6 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
index 21055e210234..c1359f4d48d7 100644
--- a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
@@ -46,6 +46,10 @@ Required properties:
0 maps to GPMC_WAIT0 pin.
- gpio-cells: Must be set to 2
+Required properties when using NAND prefetch dma:
+ - dmas GPMC NAND prefetch dma channel
+ - dma-names Must be set to "rxtx"
+
Timing properties for child nodes. All are optional and default to 0.
- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
@@ -137,7 +141,8 @@ Example for an AM33xx board:
ti,hwmods = "gpmc";
reg = <0x50000000 0x2000>;
interrupts = <100>;
-
+ dmas = <&edma 52 0>;
+ dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;