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| author |   Thierry Reding <treding@nvidia.com> | 2017-12-13 12:53:43 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 12:53:43 +0100 |
| commit | 029ab5eaf091ce5eaa1f3017f66fd1d10f431d61 (patch) | |
| tree | 0796fd5e58f51c658b08790f0769131b167fc54a /Documentation/devicetree/bindings/memory-controllers | |
| parent | dt-bindings: misc: Add Tegra186 MISC registers bindings (diff) | |
| download | linux-dev-029ab5eaf091ce5eaa1f3017f66fd1d10f431d61.tar.xz linux-dev-029ab5eaf091ce5eaa1f3017f66fd1d10f431d61.zip | |
dt-bindings: memory: Add Tegra186 support
As opposed to earlier incarnations, the memory controller on Tegra186 no
longer implements an SMMU. Instead the SMMU is a regular ARM SMMU and in
a separate IP block.
However, the memory controller programs the SMMU stream IDs for each of
the memory clients. Add a header file with definitions for each of these
stream IDs and mark the #iommu-cells property as required on Tegra30 to
Tegra210 in the device tree bindings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt index 8dbe47013c2b..14968b048cd3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt @@ -12,6 +12,8 @@ Required properties: - clock-names: Must include the following entries: - mc: the module's clock input - interrupts: The interrupt outputs from the controller. + +Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210: - #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines the SWGROUP of the master. |