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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2014-09-02 14:19:07 -0700
committerMichal Simek <michal.simek@xilinx.com>2014-09-16 12:55:05 +0200
commitc07c8b007732dacafd4ba9cda04ea9b9d0e8ec7d (patch)
tree801aa2fb8603716cc196f6ba63999f3eef37584e /Documentation/devicetree/bindings/memory-controllers
parentARM: zynq: PM: Enable A9 internal clock gating feature (diff)
downloadlinux-dev-c07c8b007732dacafd4ba9cda04ea9b9d0e8ec7d.tar.xz
linux-dev-c07c8b007732dacafd4ba9cda04ea9b9d0e8ec7d.zip
Documentation: devicetree: Add binding for Synopsys DDR controller
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/synopsys.txt11
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diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
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+Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
+
+Required properties:
+ - compatible: Should be 'xlnx,zynq-ddrc-a05'
+ - reg: Base address and size of the controllers memory area
+
+Example:
+ memory-controller@f8006000 {
+ compatible = "xlnx,zynq-ddrc-a05";
+ reg = <0xf8006000 0x1000>;
+ };