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authorJ Keerthy <j-keerthy@ti.com>2013-06-06 10:57:21 +0530
committerGrant Likely <grant.likely@linaro.org>2013-06-12 10:28:41 +0100
commit8d561b60a9174defff2e48e109f68a5f2ae7dd9c (patch)
treef1e9e7d4e2f317a5946b3daca62af493ae3f559c /Documentation/devicetree/bindings/mfd/palmas.txt
parentARM: dts: omap3-devkit8000: fix NAND memory binding (diff)
downloadlinux-dev-8d561b60a9174defff2e48e109f68a5f2ae7dd9c.tar.xz
linux-dev-8d561b60a9174defff2e48e109f68a5f2ae7dd9c.zip
mfd: DT bindings for the palmas family MFD
Add the various binding files for the palmas family of chips. There is a top level MFD binding then a seperate binding for regulators IP blocks on chips. Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk> Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Ian Lartey <ian@slimlogic.co.uk> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Grant Likely <grant.likely@linaro.org>
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+* palmas device tree bindings
+
+The TI palmas family current members :-
+twl6035 (palmas)
+twl6037 (palmas)
+tps65913 (palmas)
+tps65914 (palmas)
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035
+ ti,twl6036
+ ti,twl6037
+ ti,tps65913
+ ti,tps65914
+ ti,tps80036
+and also the generic series names
+ ti,palmas
+- interrupt-controller : palmas has its own internal IRQs
+- #interrupt-cells : should be set to 2 for IRQ number and flags
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as the trigger masks from
+ Documentation/devicetree/bindings/interrupts.txt
+- interrupt-parent : The parent interrupt controller.
+
+Optional properties:
+ ti,mux-padX : set the pad register X (1-2) to the correct muxing for the
+ hardware, if not set will use muxing in OTP.
+
+Example:
+
+palmas {
+ compatible = "ti,twl6035", "ti,palmas";
+ reg = <0x48>
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,mux-pad1 = <0>;
+ ti,mux-pad2 = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic {
+ compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+ ....
+ };
+}