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authorJisheng Zhang <Jisheng.Zhang@synaptics.com>2018-07-06 15:20:47 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2018-07-16 11:21:45 +0200
commitaaadfa66908460bb4e29eb3904b3d386e6b1835f (patch)
treeff6a048dee925545dae81067bc7f4f22c1e00dd1 /Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
parentmmc: sdhci: do not try to use 3.3V signaling if not supported (diff)
downloadlinux-dev-aaadfa66908460bb4e29eb3904b3d386e6b1835f.tar.xz
linux-dev-aaadfa66908460bb4e29eb3904b3d386e6b1835f.zip
dt: bindings: Add bindings for SDHCI Synopsys DWC MSHC
Synopsys SDHCI compatible DesignWare Cores Mobile Storage Host Controller can support eMMC/SD/SDIO. Add the bindings. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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+* Synopsys DesignWare Cores Mobile Storage Host Controller
+
+Required properties:
+- compatible: should be one of the following:
+ "snps,dwcmshc-sdhci"
+- reg: offset and length of the register set for the device.
+- interrupts: a single interrupt specifier.
+- clocks: Array of clocks required for SDHCI; requires at least one for
+ core clock.
+- clock-names: Array of names corresponding to clocks property; shall be
+ "core" for core clock and "bus" for optional bus clock.
+
+Example:
+ sdhci2: sdhci@aa0000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xaa0000 0x1000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&emmcclk>;
+ bus-width = <8>;
+ }