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authorMasahiro Yamada <yamada.masahiro@socionext.com>2018-08-23 13:44:16 +0900
committerUlf Hansson <ulf.hansson@linaro.org>2018-10-08 11:40:43 +0200
commit0196c8db8363f7627df6f78615271ae0ba430500 (patch)
tree56c60616dde400e8808c2f9a0d4acaf2df1fc307 /Documentation/devicetree/bindings/mmc/uniphier-sd.txt
parentmmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock() (diff)
downloadlinux-dev-0196c8db8363f7627df6f78615271ae0ba430500.tar.xz
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mmc: tmio: move tmio_mmc_set_clock() to platform hook
tmio_mmc_set_clock() is full of quirks because different SoC vendors extended this in different ways. The original IP defines the divisor range 1/2 ... 1/512. bit 7 is set: 1/512 bit 6 is set: 1/256 ... bit 0 is set: 1/4 all bits clear: 1/2 It is platform-dependent how to achieve the 1/1 clock. I guess the TMIO-MFD variant uses the clock selector outside of this IP, as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c I guess bit[7:0]=0xff is Renesas-specific extension. Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer versions of UniPhier SoC variants use bit 16 for 1/1024. host->clk_update() is only used by the Renesas variants, whereas host->set_clk_div() is only used by the TMIO-MFD variants. To cope with this mess, promote tmio_mmc_set_clock() to a new platform hook ->set_clock(), and melt the old two hooks into it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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