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| author |   Chaotian Jing <chaotian.jing@mediatek.com> | 2015-10-27 14:24:22 +0800 |
|---|---|---|
| committer |   Ulf Hansson <ulf.hansson@linaro.org> | 2015-10-27 10:21:15 +0100 |
| commit | 2c21d26825d5c1fda1729541d5fad56ee7ef7fa2 (patch) | |
| tree | 71640ec19da035324b40fd2fb89c013c3fda0c66 /Documentation/devicetree/bindings/mmc | |
| parent | mmc: core: Add DT bindings for eMMC hardware reset support (diff) | |
| download | linux-dev-2c21d26825d5c1fda1729541d5fad56ee7ef7fa2.tar.xz linux-dev-2c21d26825d5c1fda1729541d5fad56ee7ef7fa2.zip | |
mmc: dt-bindings: update Mediatek MMC bindings
Add 400Mhz clock source for HS400 mode
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mmc')
| -rw-r--r-- | Documentation/devicetree/bindings/mmc/mtk-sd.txt | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index a1adfa495ad3..0120c7f1109c 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -17,6 +17,11 @@ Required properties: - vmmc-supply: power to the Core - vqmmc-supply: power to the IO +Optional properties: +- assigned-clocks: PLL of the source clock +- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock +- hs400-ds-delay: HS400 DS delay setting + Examples: mmc0: mmc@11230000 { compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc"; @@ -24,9 +29,13 @@ mmc0: mmc@11230000 { interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; vmmc-supply = <&mt6397_vemc_3v3_reg>; vqmmc-supply = <&mt6397_vio18_reg>; - clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC50_0_H_SEL>; clock-names = "source", "hclk"; pinctrl-names = "default", "state_uhs"; pinctrl-0 = <&mmc0_pins_default>; pinctrl-1 = <&mmc0_pins_uhs>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + hs400-ds-delay = <0x14015>; }; |