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| author |   Bin Meng <bmeng.cn@gmail.com> | 2017-09-11 02:42:00 -0700 |
|---|---|---|
| committer |   Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> | 2017-10-11 09:57:50 +0200 |
| commit | 3163d125b7b1f9c6844fc3448f8080ad268a8f63 (patch) | |
| tree | 2a29af22767ab6b8e653e319040b24ca8b8c8032 /Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | |
| parent | spi-nor: intel-spi: Rename swseq to swseq_reg in 'struct intel_spi' (diff) | |
| download | linux-dev-3163d125b7b1f9c6844fc3448f8080ad268a8f63.tar.xz linux-dev-3163d125b7b1f9c6844fc3448f8080ad268a8f63.zip | |
spi-nor: intel-spi: Fall back to use SW sequencer to erase
According to the datasheet, the HW sequencer has a predefined list
of opcodes, with only the erase opcode being programmable in LVSCC
and UVSCC registers. If these registers don't contain a valid erase
opcode (eg: BIOS does not program it), erase cannot be done using
the HW sequencer, even though the erase operation does not report
any error, the flash remains not erased.
If such register setting is detected, let's fall back to use the SW
sequencer to erase instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Diffstat (limited to 'Documentation/devicetree/bindings/mtd/cadence-quadspi.txt')
0 files changed, 0 insertions, 0 deletions