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authorGabriele Paoloni <gabriele.paoloni@huawei.com>2015-09-29 00:03:10 +0800
committerBjorn Helgaas <bhelgaas@google.com>2015-11-02 14:48:45 -0600
commit907fce0902539ecde609e485eb2ecd7119a7a623 (patch)
tree158e8616fa813e0d0e2aa9a285f9de0f22317143 /Documentation/devicetree/bindings/pci/designware-pcie.txt
parentPCI: designware: Require config accesses to be naturally aligned (diff)
downloadlinux-dev-907fce0902539ecde609e485eb2ecd7119a7a623.tar.xz
linux-dev-907fce0902539ecde609e485eb2ecd7119a7a623.zip
PCI: designware: Make "num-lanes" an optional DT property
Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used if we call dw_pcie_setup_rc() while bringing up the link. If the link has already been brought up by firmware, we need not call dw_pcie_setup_rc(), and "num-lanes" is unnecessary. Only complain about "num-lanes" if we actually need it and we didn't find a valid value. [bhelgaas: changelog] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/designware-pcie.txt')
-rw-r--r--Documentation/devicetree/bindings/pci/designware-pcie.txt3
1 files changed, 2 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 9f4faa8e8d00..0036ab3065b8 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -14,7 +14,6 @@ Required properties:
- interrupt-map-mask and interrupt-map: standard PCI properties
to define the mapping of the PCIe interface to interrupt
numbers.
-- num-lanes: number of lanes to use
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
@@ -22,6 +21,8 @@ Required properties:
- "pcie_bus"
Optional properties:
+- num-lanes: number of lanes to use (this property should be specified unless
+ the link is brought already up in BIOS)
- reset-gpio: gpio pin number of power good signal
- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
specify this property, to keep backwards compatibility a range of 0x00-0xff