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| author |   Conor Dooley <conor.dooley@microchip.com> | 2022-08-20 00:14:11 +0100 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lpieralisi@kernel.org> | 2022-08-24 13:38:26 +0200 |
| commit | 05a5741019a524ab9e1d355528c8ebcbd6debfe7 (patch) | |
| tree | e3f54903a7d3b3f74618b620a75beff4242025ef /Documentation/devicetree/bindings/pci | |
| parent | dt-bindings: PCI: fu740-pci: fix missing clock-names (diff) | |
| download | linux-dev-05a5741019a524ab9e1d355528c8ebcbd6debfe7.tar.xz linux-dev-05a5741019a524ab9e1d355528c8ebcbd6debfe7.zip | |
dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties
Recent versions of dt-schema warn about unevaluatedProperties:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected)
From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
The clocks are required to enable interfaces between the FPGA fabric
and the core complex, so add them to the binding.
Link: https://lore.kernel.org/r/20220819231415.3860210-3-mail@conchuod.ie
Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index edb4f81253c8..6fbe62f4da93 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -25,6 +25,33 @@ properties: - const: cfg - const: apb + clocks: + description: + Fabric Interface Controllers, FICs, are the interface between the FPGA + fabric and the core complex on PolarFire SoC. The FICs require two clocks, + one from each side of the interface. The "FIC clocks" described by this + property are on the core complex side & communication through a FIC is not + possible unless it's corresponding clock is enabled. A clock must be + enabled for each of the interfaces the root port is connected through. + This could in theory be all 4 interfaces, one interface or any combination + in between. + minItems: 1 + items: + - description: FIC0's clock + - description: FIC1's clock + - description: FIC2's clock + - description: FIC3's clock + + clock-names: + description: + As any FIC connection combination is possible, the names should match the + order in the clocks property and take the form "ficN" where N is a number + 0-3 + minItems: 1 + maxItems: 4 + items: + pattern: '^fic[0-3]$' + interrupts: minItems: 1 items: |