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| author |   Niklas Cassel <niklas.cassel@axis.com> | 2017-12-20 00:29:38 +0100 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2017-12-21 11:10:35 +0000 |
| commit | 4c3f9e9cfe5ddacd2af978043056767ac0bb00d2 (patch) | |
| tree | c4143e2650bbed9a1c875f7d58639a41e7b1fc09 /Documentation/devicetree/bindings/pci | |
| parent | PCI: dwc: artpec6: Deassert the core before waiting for PHY (diff) | |
| download | linux-dev-4c3f9e9cfe5ddacd2af978043056767ac0bb00d2.tar.xz linux-dev-4c3f9e9cfe5ddacd2af978043056767ac0bb00d2.zip | |
bindings: PCI: artpec: Add support for the ARTPEC-7 SoC
Add support for the ARTPEC-7 SoC in the artpec6 driver.
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt index 33eef7ae5a23..979dc7b6cfe8 100644 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt @@ -6,6 +6,8 @@ and thus inherits all the common properties defined in designware-pcie.txt. Required properties: - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; + "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; + "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; - reg: base addresses and lengths of the PCIe controller (DBI), the PHY controller, and configuration address space. - reg-names: Must include the following entries: |