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authorSean Cross <xobs@kosagi.com>2013-09-26 11:24:47 +0800
committerBjorn Helgaas <bhelgaas@google.com>2013-09-27 13:17:08 -0600
commitbb38919ec56e0758c3ae56dfc091dcde1391353e (patch)
tree2bfadf7af2bd93e9d34b6a69bdae085bac7b3df9 /Documentation/devicetree/bindings/pci
parentARM: imx6q: Add PCIe bits to GPR syscon definition (diff)
downloadlinux-dev-bb38919ec56e0758c3ae56dfc091dcde1391353e.tar.xz
linux-dev-bb38919ec56e0758c3ae56dfc091dcde1391353e.zip
PCI: imx6: Add support for i.MX6 PCIe controller
Add support for the PCIe port present on the i.MX6 family of controllers. These use the Synopsis Designware core tied to their own PHY. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
-rw-r--r--Documentation/devicetree/bindings/pci/designware-pcie.txt7
1 files changed, 6 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index eabcb4b5db6e..dd8d920bcbd6 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -3,7 +3,7 @@
Required properties:
- compatible: should contain "snps,dw-pcie" to identify the
core, plus an identifier for the specific instance, such
- as "samsung,exynos5440-pcie".
+ as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
- interrupts: interrupt values for level interrupt,
@@ -21,6 +21,11 @@ Required properties:
- num-lanes: number of lanes to use
- reset-gpio: gpio pin number of power good signal
+Optional properties for fsl,imx6q-pcie
+- power-on-gpio: gpio pin number of power-enable signal
+- wake-up-gpio: gpio pin number of incoming wakeup signal
+- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
+
Example:
SoC specific DT Entry: