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| author |   Niklas Cassel <niklas.cassel@axis.com> | 2017-12-20 00:29:34 +0100 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2017-12-21 11:10:33 +0000 |
| commit | dff9cba6f8ef2fe26dadbaebacc7cbf7ed50a327 (patch) | |
| tree | 8b7020b017bc4f0073894fca008fb48b071b8347 /Documentation/devicetree/bindings/pci | |
| parent | PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functions (diff) | |
| download | linux-dev-dff9cba6f8ef2fe26dadbaebacc7cbf7ed50a327.tar.xz linux-dev-dff9cba6f8ef2fe26dadbaebacc7cbf7ed50a327.zip | |
bindings: PCI: artpec: Add support for endpoint mode
The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in
endpoint mode. Add endpoint mode support to the artpec6 driver.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt index 4e4aee4439ea..33eef7ae5a23 100644 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "axis,artpec6-pcie", "snps,dw-pcie" +- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; + "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; - reg: base addresses and lengths of the PCIe controller (DBI), the PHY controller, and configuration address space. - reg-names: Must include the following entries: |