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| author |   Icenowy Zheng <icenowy@aosc.xyz> | 2017-03-25 22:50:08 +0800 |
|---|---|---|
| committer |   Kishon Vijay Abraham I <kishon@ti.com> | 2017-04-10 16:42:57 +0530 |
| commit | a0b1910e857897ae6c420fa0ece52c87d7cff373 (patch) | |
| tree | 81a669be7e90967455eb067dd61fa863b23c24e4 /Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | |
| parent | mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header (diff) | |
| download | linux-dev-a0b1910e857897ae6c420fa0ece52c87d7cff373.tar.xz linux-dev-a0b1910e857897ae6c420fa0ece52c87d7cff373.zip | |
dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.
When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index e42334258185..005bc22938ff 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -15,6 +15,7 @@ Required properties: - reg : a list of offset + length pairs - reg-names : * "phy_ctrl" + * "pmu0" for H3, V3s and A64 * "pmu1" * "pmu2" for sun4i, sun6i or sun7i - #phy-cells : from the generic phy bindings, must be 1 |