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author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-04 11:05:48 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-04 11:05:48 -0700 |
commit | 228dfe98a313f6b6bff5da8b2c5e650e297ebf1a (patch) | |
tree | 501dc44c2453743eb2298fe23d6cdd0b5e91b2c2 /Documentation/devicetree/bindings/phy | |
parent | drm/amd/display: restore code for plane with no modifiers (diff) | |
parent | drivers: lkdtm: fix clang -Wformat warning (diff) | |
download | linux-dev-228dfe98a313f6b6bff5da8b2c5e650e297ebf1a.tar.xz linux-dev-228dfe98a313f6b6bff5da8b2c5e650e297ebf1a.zip |
Merge tag 'char-misc-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char / misc driver updates from Greg KH:
"Here is the large set of char and misc and other driver subsystem
changes for 6.0-rc1.
Highlights include:
- large set of IIO driver updates, additions, and cleanups
- new habanalabs device support added (loads of register maps much
like GPUs have)
- soundwire driver updates
- phy driver updates
- slimbus driver updates
- tiny virt driver fixes and updates
- misc driver fixes and updates
- interconnect driver updates
- hwtracing driver updates
- fpga driver updates
- extcon driver updates
- firmware driver updates
- counter driver update
- mhi driver fixes and updates
- binder driver fixes and updates
- speakup driver fixes
All of these have been in linux-next for a while without any reported
problems"
* tag 'char-misc-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (634 commits)
drivers: lkdtm: fix clang -Wformat warning
char: remove VR41XX related char driver
misc: Mark MICROCODE_MINOR unused
spmi: trace: fix stack-out-of-bound access in SPMI tracing functions
dt-bindings: iio: adc: Add compatible for MT8188
iio: light: isl29028: Fix the warning in isl29028_remove()
iio: accel: sca3300: Extend the trigger buffer from 16 to 32 bytes
iio: fix iio_format_avail_range() printing for none IIO_VAL_INT
iio: adc: max1027: unlock on error path in max1027_read_single_value()
iio: proximity: sx9324: add empty line in front of bullet list
iio: magnetometer: hmc5843: Remove duplicate 'the'
iio: magn: yas530: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
iio: magnetometer: ak8974: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
iio: light: veml6030: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
iio: light: vcnl4035: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
iio: light: vcnl4000: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
iio: light: tsl2591: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr()
iio: light: tsl2583: Use DEFINE_RUNTIME_DEV_PM_OPS and pm_ptr()
iio: light: isl29028: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr()
iio: light: gp2ap002: Switch to DEFINE_RUNTIME_DEV_PM_OPS and pm_ptr()
...
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
12 files changed, 215 insertions, 10 deletions
diff --git a/Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml b/Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml new file mode 100644 index 000000000000..7aa0c05d6ce4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic G12A MIPI analog PHY + +maintainers: + - Neil Armstrong <narmstrong@baylibre.com> + +properties: + compatible: + const: amlogic,g12a-mipi-dphy-analog + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@0 { + compatible = "amlogic,g12a-mipi-dphy-analog"; + reg = <0x0 0xc>; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index c50629bd1b51..f0e9ca8427bb 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -11,8 +11,9 @@ maintainers: properties: compatible: - items: - - const: cdns,dphy + enum: + - cdns,dphy + - ti,j721e-dphy reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml new file mode 100644 index 000000000000..8767e48c71a6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mixel LVDS PHY for Freescale i.MX8qm SoC + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +description: | + The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC. + It converts two groups of four 7/10 bits of CMOS data into two + groups of four data lanes of LVDS data streams. A phase-locked + transmit clock is transmitted in parallel with each group of + data streams over a fifth LVDS link. Every cycle of the transmit + clock, 56/80 bits of input data are sampled and transmitted + through the two groups of LVDS data streams. Together with the + transmit clocks, the two groups of LVDS data streams form two + LVDS channels. + + The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled + by Control and Status Registers(CSR) module in the SoC. The CSR + module, as a system controller, contains the PHY's registers. + +properties: + compatible: + enum: + - fsl,imx8qm-lvds-phy + - mixel,28fdsoi-lvds-1250-8ch-tx-pll + + "#phy-cells": + const: 1 + description: | + Cell allows setting the LVDS channel index of the PHY. + Index 0 is for LVDS channel0 and index 1 is for LVDS channel1. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - "#phy-cells" + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/firmware/imx/rsrc.h> + phy { + compatible = "fsl,imx8qm-lvds-phy"; + #phy-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index 6e4d795f9b02..9c2a7345955d 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -24,6 +24,10 @@ properties: - enum: - mediatek,mt7623-mipi-tx - const: mediatek,mt2701-mipi-tx + - items: + - enum: + - mediatek,mt8365-mipi-tx + - const: mediatek,mt8183-mipi-tx - const: mediatek,mt2701-mipi-tx - const: mediatek,mt8173-mipi-tx - const: mediatek,mt8183-mipi-tx diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml new file mode 100644 index 000000000000..422750cc4121 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIe PHY + +maintainers: + - Jianjun Wang <jianjun.wang@mediatek.com> + +description: | + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. + +properties: + compatible: + const: mediatek,mt8195-pcie-phy + + reg: + maxItems: 1 + + reg-names: + items: + - const: sif + + "#phy-cells": + const: 0 + + nvmem-cells: + maxItems: 7 + description: + Phandles to nvmem cell that contains the efuse data, if unspecified, + default value is used. + + nvmem-cell-names: + items: + - const: glb_intr + - const: tx_ln0_pmos + - const: tx_ln0_nmos + - const: rx_ln0 + - const: tx_ln1_pmos + - const: tx_ln1_nmos + - const: rx_ln1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + #phy-cells = <0>; + reg = <0x11e80000 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, + <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, + <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, + <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains = <&spm 2>; + }; diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 7b2e1bc119be..b3e409988c17 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -82,9 +82,11 @@ properties: - mediatek,mt8183-tphy - mediatek,mt8186-tphy - mediatek,mt8192-tphy + - mediatek,mt8365-tphy - const: mediatek,generic-tphy-v2 - items: - enum: + - mediatek,mt8188-tphy - mediatek,mt8195-tphy - const: mediatek,generic-tphy-v3 - const: mediatek,mt2701-u3phy diff --git a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt index c9f5c0caf8a9..c9e392c64a7c 100644 --- a/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/mxs-usb-phy.txt @@ -8,6 +8,7 @@ Required properties: * "fsl,vf610-usbphy" for Vybrid vf610 * "fsl,imx6sx-usbphy" for imx6sx * "fsl,imx7ulp-usbphy" for imx7ulp + * "fsl,imx8dxl-usbphy" for imx8dxl "fsl,imx23-usbphy" is still a fallback for other strings - reg: Should contain registers location and length - interrupts: Should contain phy interrupt diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml index 9a89d05efbda..4dc5205d893b 100644 --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: NVIDIA Tegra194 P2U binding +title: NVIDIA Tegra194 & Tegra234 P2U binding maintainers: - Thierry Reding <treding@nvidia.com> @@ -12,13 +12,17 @@ maintainers: description: > Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High Speed) each interfacing with 12 and 8 P2U instances respectively. + Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet) + each interfacing with 8, 8 and 8 P2U instances respectively. A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE - interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe - lane. + interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one + PCIe lane. properties: compatible: - const: nvidia,tegra194-p2u + enum: + - nvidia,tegra194-p2u + - nvidia,tegra234-p2u reg: maxItems: 1 @@ -28,6 +32,11 @@ properties: items: - const: ctl + nvidia,skip-sz-protect-en: + description: Should be present if two PCIe retimers are present between + the root port and its immediate downstream device. + type: boolean + '#phy-cells': const: 0 diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index a5850ff529f8..cf9e9b8011cb 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -41,6 +41,9 @@ properties: "#phy-cells": const: 0 + vdda-phy-supply: true + vdda-pll-supply: true + required: - compatible - reg @@ -65,5 +68,8 @@ examples: #clock-cells = <1>; #phy-cells = <0>; + + vdda-phy-supply = <&vdd_a_edp_0_1p2>; + vdda-pll-supply = <&vdd_a_edp_0_0p9>; }; ... diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 8b850c5ab116..220788ce215f 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,ipq6018-qmp-pcie-phy - qcom,ipq6018-qmp-usb3-phy + - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy - qcom,ipq8074-qmp-usb3-phy - qcom,msm8996-qmp-pcie-phy @@ -312,6 +313,7 @@ allOf: contains: enum: - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy then: properties: diff --git a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml index b8483f9edbfc..fe57c5373d18 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml @@ -34,7 +34,7 @@ properties: # must not be 0. minItems: 2 items: - - const: usb3-if # The funcional clock + - const: usb3-if # The functional clock - const: usb3s_clk # The usb3's external clock - const: usb_extal # The usb2's external clock diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml index f6ed1a005e7a..8da99461e817 100644 --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml @@ -17,6 +17,7 @@ properties: enum: - samsung,exynos7-ufs-phy - samsung,exynosautov9-ufs-phy + - tesla,fsd-ufs-phy reg: maxItems: 1 @@ -40,9 +41,17 @@ properties: - const: tx0_symbol_clk samsung,pmu-syscon: - $ref: '/schemas/types.yaml#/definitions/phandle' - description: phandle for PMU system controller interface, used to - control pmu registers bits for ufs m-phy + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + items: + minItems: 1 + items: + - description: phandle for PMU system controller interface, used to + control pmu registers bits for ufs m-phy + - description: offset of the pmu control register + description: + It can be phandle/offset pair. The second cell which can represent an + offset is optional. required: - "#phy-cells" |