Merge tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next

Pull pin control changes from Linus Walleij:
 "This is the bulk of pin control changes for the v3.16 development
  cycle:

   - Antoine Tenart made the get_group_pins() vtable entry optional.

   - Antoine also provides an entirely new driver for the Marvell Berlin
     SoC.  This is unrelated to the existing MVEBU hardware driver and
     warrants its own separate driver.

   - reflected from the GPIO subsystem there is a number of refactorings
     to make pin control drivers with gpiochips use the new gpiolib
     irqchip helpers.  The following drivers were converted to use the
     new infrastructure:
       * ST Microelectronics STiH416 and friends
       * The Atmel AT91
       * The CSR SiRF (Prima2)
       * The Qualcomm MSM series

   - massive improvements in the Qualcomm MSM driver from Bjorn
     Andersson, Andy Gross and Kumar Gala.  Among those new support for
     the IPQ8064 and MSM8x74 SoC variants.

   - support for the Freescale i.MX6 SoloX SoC variant.

   - massive improvements in the Allwinner sunxi driver from Boris
     Brezillon, Maxime Ripard and Chen-Yu Tsai.

   - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto,
     Wolfram Sang and Magnus Damm.

   - Cleanups and refactorings of the nVidia Tegra driver from Stepgen
     Warren.

   - the Exynos driver now supports the Exynos3250 SoC.

   - Intel BayTrail updates from Jin Yao, Mika Westerberg.

   - the MVEBU driver now supports the Orion5x SoC variants, which is
     part of the effort of getting rid of the old Marvell kludges in
     arch/arm/mach-orion5x

   - Rockchip driver updates from Heiko Stuebner.

   - a ton of cleanups and janitorial patches from Axel Lin.

   - some minor fixes and improvements here and there"

* tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits)
  pinctrl: sirf: fix a bad conflict resolution
  pinctrl: msm: Add more MSM8X74 pin definitions
  pinctrl: qcom: ipq8064: Fix naming convention
  pinctrl: msm: Add missing sdc1 and sdc3 groups
  pinctrl: sirf: switch to using allocated state container
  pinctrl: Enable "power-source" to be extracted from DT files
  pinctrl: sunxi: create irq/pin mapping during init
  pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy
  pinctrl: berlin: Use devm_ioremap_resource()
  pinctrl: sirf: fix typo for GPIO bank number
  pinctrl: sunxi: depend on RESET_CONTROLLER
  pinctrl: sunxi: fix pin numbers passed to register offset helpers
  pinctrl: add pinctrl driver for imx6sx
  pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs
  pinctrl: msm: switch to using generic GPIO irqchip helpers
  pinctrl: sunxi: Fix multiple registration issue
  pinctrl: sunxi: Fix recursive dependency
  pinctrl: berlin: add the BG2CD pinctrl driver
  pinctrl: berlin: add the BG2 pinctrl driver
  pinctrl: berlin: add the BG2Q pinctrl driver
  ...

1 files changed, 36 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
new file mode 100644
index 000000000000..b1b595220f1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
@@ -0,0 +1,36 @@
+* Freescale i.MX6 SoloX IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx6sx-iomuxc"
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val
+  input_val> are specified using a PIN_FUNC_ID macro, which can be found in
+  imx6sx-pinfunc.h under device tree source folder.  The last integer CONFIG is
+  the pad setting value like pull-up on this pin.  Please refer to i.MX6 SoloX
+  Reference Manual for detailed CONFIG settings.
+
+CONFIG bits definition:
+PAD_CTL_HYS                     (1 << 16)
+PAD_CTL_PUS_100K_DOWN           (0 << 14)
+PAD_CTL_PUS_47K_UP              (1 << 14)
+PAD_CTL_PUS_100K_UP             (2 << 14)
+PAD_CTL_PUS_22K_UP              (3 << 14)
+PAD_CTL_PUE                     (1 << 13)
+PAD_CTL_PKE                     (1 << 12)
+PAD_CTL_ODE                     (1 << 11)
+PAD_CTL_SPEED_LOW               (0 << 6)
+PAD_CTL_SPEED_MED               (1 << 6)
+PAD_CTL_SPEED_HIGH              (3 << 6)
+PAD_CTL_DSE_DISABLE             (0 << 3)
+PAD_CTL_DSE_260ohm              (1 << 3)
+PAD_CTL_DSE_130ohm              (2 << 3)
+PAD_CTL_DSE_87ohm               (3 << 3)
+PAD_CTL_DSE_65ohm               (4 << 3)
+PAD_CTL_DSE_52ohm               (5 << 3)
+PAD_CTL_DSE_43ohm               (6 << 3)
+PAD_CTL_DSE_37ohm               (7 << 3)
+PAD_CTL_SRE_FAST                (1 << 0)
+PAD_CTL_SRE_SLOW                (0 << 0)